`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   01:22:42 04/01/2013
// Design Name:   seg_display
// Module Name:   C:/Users/jimmy/Documents/2013/CSE 320/lab2/FIFO1/tb/tb_segdisplay.v
// Project Name:  FIFO1
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: seg_display
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_segdisplay;

	// Inputs
	reg clk;
	reg reset_b;
	reg reg_read;
	reg [1:0] reg_addr;

	// Outputs
	wire [3:0] reg_data;
	wire dp_dis;
	wire [3:0] dis_control;
	wire [6:0] led_dis;

	// Instantiate the Unit Under Test (UUT)
	seg_display uut (
		.clk(clk), 
		.reset_b(reset_b), 
		.reg_read(reg_read), 
		.reg_addr(reg_addr), 
		.reg_data(reg_data), 
		.dp_dis(dp_dis), 
		.dis_control(dis_control), 
		.led_dis(led_dis)
	);
	
	
		initial begin
		forever #5 clk <= ~clk;
		end

	initial begin
		// Initialize Inputs
		clk = 0;
		reset_b = 0;
		reg_read = 0;
		reg_addr = 0;

		// Wait 100 ns for global reset to finish
		
		reset_b = 1'b1;;
		// Add stimulus here

	end
      
endmodule

